The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. However, continued scaling of FinFET devices requires concurrent improvements in photolithographic processes. Current lithography techniques may be limited, for example, in their alignment precision and repeatability of the equipment used (e.g., a photolithography stepper), as well as in the minimum feature size that may be printed. Thus, current lithography tools may not provide sufficient process margin, in particular when employing existing photolithography processes. As a result, FinFET critical dimensions (CDs) may be directly impacted by pattern misalignment, or other lithography errors, which can result in degraded device performance and/or device failure. Thus, existing techniques have not proved entirely satisfactory in all respects.